Nanyang Technological University, Singapore
It is my honor to be the editor-in-chief of IJEETC. The journal publishes good papers which focous on the advanced researches in the field of electrical and electronic engineering & telecommunications.
Abstract— The most area and power consuming arithmetic operation in high-performance circuits like Finite Impulse Response (FIR), multiplication is one. There are different types of multipliers to reducing the cost and effective parameters in FIR filter design. Among those this paper use truncated multiplier and modified Wallace multiplier in the fir design. The structural adders and delay elements occupies more area and consumes power in this form so it was a reason to forward the proposed method. In prior FIR filters design with low cost effective results will done by the faithfully rounded truncated multipliers with the carry save additions. In MCMAT design the low cost FIR filters within the best area and power results are implement in this paper by using the improved truncated methods. Along with that the proposed method modified Wallace multiplier based fir filter is also designed in this paper to make the fir filter design is suitable for low power applications.
Index Terms— Finite Impulse Response (FIR) Filter, Multiple constant multipliers/Accumulators with faithfully rounded truncation (MCMAT), Truncated multiplier, MODIFIED WALLACE tree multiplier
Cite: Nakka Sivaraju and S Suman, "AREA POWER AND DELAY EFFICIENT EVALUATION OF TRUNCATED AND MODIFIED WALLACE FIR FILTER," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 4, No. 4, pp. 43-52, October 2015.
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