Nanyang Technological University, Singapore
It is my honor to be the editor-in-chief of IJEETC. The journal publishes good papers which focous on the advanced researches in the field of electrical and electronic engineering & telecommunications.
Abstract— Low power design has been an important part in VLSI system design. Digital multipliers are most critical functional units of digital filters. The overall performance of digital filters depends on the throughput of multiplier design. Aging problem of transistors has a significant effect on performance of these systems and in long term, the system may fail due to delay problems. Aging effect can be reduced by using over-design approaches, but these approaches leads to area, power inefficiency. Moreover, timing violations occur when fixed latency designs are used. Hence to reduce timing violations and to ensure reliable operation under aging effect, low power variable latency multiplier with adaptive hold logic is used. Negative bias and positive bias temperature both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose a Vedic multiplier design with a razor based multiplier circuit. This design is able to provide higher throughput through the area and power efficiency enhancement than the existing Column By passing multiplier. This multiplier design can be applied to digital filters so as to enhance its performance in the real time environment.
Index Terms— Aging Effect, Vedic Multiplier, Razor Flipflops, AHL
Cite: Ch Pavan Mohan and M Sumalatha, "REALIZATION OF LOW POWER AND AREA REDUCED AGING-AWARE MULTIPLIER DESIGN," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 4, No. 4, pp. 53-61, October 2015.
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