Home > Published Issues > 2015 > Volume 4, No. 4, October 2015 >


Samuel Challapalli and N Suresh Babu
Department of ECE, Chirala Engineering College, Chirala, Andhra Pradesh 523157, India

Abstract— As modern computing systems become increasingly complex, communication efficiency among and inside chips has become as important as the computation speeds of individual processor cores. Traditionally, inter-chip and intra-chip communication architectures are separately designed to maximize design flexibility under different constraints. However, jointly designing communication architectures for both inter-chip and intra-chip communication could potentially yield better solutions. In this project, we present an inter/intra-chip optical network, called I2CON, for chip multiprocessors (CMP). I2CON is based on recent progress in nano-photonic technologies. It connects not only processors on a single CMP but also multiple CMPs in a system. I2CON employs a hierarchical optical network to separate inter-chip communication traffic from intra-chip communication traffic. It fully utilizes a single optical network to transmit both payload packets and control packets. The network controller on each CMP not only manages intra-chip communications but also collaborate with each other to facilitate inter-chip communications. By using the proper FSM we prove the communication is happen in the entire chip with reduced power consumption.

Index Terms— I2CON, chip multiprocessors (CMP), NOC, Power consumption

Cite: Samuel Challapalli and N Suresh Babu, "IMPLEMENTATION OF POWER OPTIMIZED I2CON FOR EFFICIENT DATA TRANSMISSION," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 4, No. 4, pp. 31-42, October 2015.