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IJEETC 2023 Vol.12(4): 235-244
doi: 10.18178/ijeetc.12.4.235-244

A Novel Design of Hilbert Huang Based All Digital Phase Locked Loop Using FPGA

Velamarthi Spandana* and Chandra Sekhar Paidimarry
Department of Electronics and Communication, Osmania University, Hyderabad, Telangana-500007, India

Manuscript received December 26, 2022; revised February 17, 2023; accepted April 6, 2023.

Abstract—Many applications for digital processing are steadily increasing in radio frequency signal processing from analog to digital. ADPLL plays a vital role in digital signal processing. Several ADPLL models were introduced in the past. However, in those models, the power dissipation gets increased due to the delay in the lock state. Due to the generated digital noise, the system leads the output signal with inherent phase noise and does not undergo the frequency division process. Therefore, a novel Hilbert-Huang based All Digital Phase Locked Loop (HH-ADPLL) was proposed to make the ADPLL into the locked state. The input reference signal is initially entered in the Hilbert-Huang transform to extract the analytic component and generate the up and down signals. By eliminating the higher frequency part from these signals, the up/down counter produces borrow and carry signals. The carry and borrow signals are fed into the increment decrement counter to produce the output signal. At last, input and output signal matching is carried out in the phase detector module, and ADPLL enters a locked state. The presented HH-ADPLL is implemented in Artix-7 FPGA, and the efficiency is validated in terms of stability, phase error, power dissipation, combinational delay, and performance improvement computed.

Index Terms—All digital phase locked loop, digital controlled oscillator, field programmable gate array, Hilbert-Huang transforms, phase detector

Cite:Velamarthi Spandana and Chandra Sekhar Paidimarry, "A Novel Design of Hilbert Huang Based All Digital Phase Locked Loop Using FPGA," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 12, No. 4, pp. 235-244, July 2023. Doi: 10.18178/ijeetc.12.4.235-244

Copyright © 2023 by the authors. This is an open access article distributed under the Creative Commons Attribution License (CC BY-NC-ND 4.0), which permits use, distribution and reproduction in any medium, provided that the article is properly cited, the use is non-commercial and no modifications or adaptations are made.