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IJEETC 2023 Vol.12(1): 46-52
doi: 10.18178/ijeetc.12.1.46-52

An Ultra-High Throughput and Efficient Implementation of Advanced Encryption Standard

Sarita Sanap 1 and Vijayshree More2
1. Maharashtra Institute of Technology, Dr. B.A.M. University, Aurangabad, India
2. Jawaharlal Nehru Engineering College, MGM University, Aurangabad, India

Manuscript received June 15, 2022; revised August 18, 2022; accepted September 18, 2022.

Abstract—Encryption techniques have become most important in the digital world. Advanced Encryption Standard implementation enhances security. In this proposed work, advanced encryption standard implementation is done on field programmable gate array through minimum resource utilization. Experimental results obtained gives area-efficient, high-throughput hardware structure. To achieve a high throughput rate and minimize resource allocation, parallel-pipeline design and data forwarding mechanism with optimized S-box is proposed. Comparison between proposed work and existing work shows that this optimized implementation gives reduction in resources and increase in throughput. Proposed method achieves throughput of 97.11Gbps and efficiency of 85.18 Mbps/slice.
Index Terms—Field programmable gate array, avalanche effect, throughput

Cite: Sarita Sanap and Vijayshree More, "An Ultra-High Throughput and Efficient Implementation of Advanced Encryption Standard," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 12, No. 1, pp. 46-52, January 2023. Doi: 10.18178/ijeetc.12.1.46-52

Copyright © 2023 by the authors. This is an open access article distributed under the Creative Commons Attribution License (CC BY-NC-ND 4.0), which permits use, distribution and reproduction in any medium, provided that the article is properly cited, the use is non-commercial and no modifications or adaptations are made.