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Design of Partial Discharge Real-Time Capture System

Yu-En Wu
National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan

Abstract—This paper presents an online partial discharge real-time capture system whose system architecture includes Field-programmable Gate Array (FPGA) components, a Human–Machine Interface (HMI), and analog amplifying circuits. The analog amplify circuit is designed to achieve a magnification rate of 10 times and a bandwidth of 100 MHz. The software developed in this work can be used for real-time online monitoring, recording, and analysis of partial discharge. The captured signal of the partial discharge was analyzed by the FPGA by using a fast Fourier transform, time–frequency map, and phase-resolved partial discharge, and the results were transmitted through the RS-232 to the HMI for display. System stability is improved through data analysis to determine possible causes of partial discharge, averting both user risk and damage to equipment.
Index Terms—Field-programmable gate array, partial discharge, real-time online monitoring

Cite: Yu-En Wu, "Design of Partial Discharge Real-Time Capture System," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 9, No. 5, pp. 342-348, September 2020. Doi: 10.18178/ijeetc.9.5.342-348

Copyright © 2020 by the authors. This is an open access article distributed under the Creative Commons Attribution License (CC BY-NC-ND 4.0), which permits use, distribution and reproduction in any medium, provided that the article is properly cited, the use is non-commercial and no modifications or adaptations are made.