Nanyang Technological University, Singapore
It is my honor to be the editor-in-chief of IJEETC. The journal publishes good papers which focous on the advanced researches in the field of electrical and electronic engineering & telecommunications.
Abstract—The two main sources of power dissipation in CMOS circuits are static current, which results
from resistive paths between power supply and ground, and dynamic power, which results from
switching capacitive loads between different voltage levels. Reducing power dissipation has
become an important objective in the design of digital circuits. Because, for every 10 °C increase
in operating temperature a component’ s failure rate is doubled. In this context, peak power for
maximum possible power dissipation is a critical design factor as it determines the thermal and
electrical limits of designs, impacts the system cost, size and weight, dictates specific battery
type, component and system packaging and heat sinks, and aggravates the resistive and
inductive voltage drop problems. It is therefore essential to have the peak power under control.
The cross talk is dependent on the data transition patterns on the bus. The fact that power
dissipation due to coupling transitions, is appreciably more (75%) than that due to self transitions
(25%), necessitates the need for reducing the number of coupling transitions also. This makes
the Bus Invert method incomplete in reducing the power dissipation. The simulation results of
our work shows that the power dissipation in a bus is reduced about 28.02% with the proposed
bus encoding technique.
Index Terms—DSM, VLSI, Self transitions, Coupling transitions, CODEC
Cite: K Padmapriya, "MODIFIED BUS INVERT TECHNIQUE FOR LOW POWER VLSI DESIGN IN DSM TECHNOLOGY," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 2, No. 2, pp. 54-57, April 2013.
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