Abstract—In this paper, we propose a new paradigm that is a power efficient and low area Vedic multiplier to meet the demand of high precision and low power integrating with the Algorithmic Noise Tolerant (ANT) architecture. The truncation errors can be decreased by implementing ancient Vedic multiplication techniques combined with modern probability and statistics method. The hardware complexity of multiplier is greatly simplified. In this 12*12 bit Vedic multiplier, the effective total on-chip power can be decreased by 15% and the circuit area in our proposed design is lowered by 25% compared with existing fixed width RPR multiplier. Hence the power is efficiently used and implemented.

Index Terms—Vedic multiplier, ANT architecture, Truncation errors

Cite: Bala Kiran P and Padma Priya K, "IMPLEMENTATION OF POWER EFFICIENT 12-BIT VEDIC MULTIPLIER BY USING ANT ARCHITECTURE," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 5, No. 4, pp. 28-36, October 2016.