Abstract—In any VLSI technique, dynamic power consumption and delay plays a very significant role in an integrated circuit design. We implement a new method for distributing the clock in a clock distribution network from a common point to all the elements equally. A current mode signalling scheme has been used in one-to-many transitions, which is implemented in this method. To attain this, we implement a high performance Clock Paired Shared Flip Flop (CPSFF). When the CPSFF is integrated with the current mode transmitter, the Clock Distribution Network (CDN) exhibits 25% amount of lower average power consumption when compared with previously implemented Current Mode Pulsed Flip Flop with Enable (CMPFFE) clock distribution network. The project is implemented in 45 nm CMOS technology so that the parameters area and delay are greatly reduced to the extent.

Index Terms—CMPFFE, CPSFF, Power gating technique, Clock distribution network, Current mode

Cite: Kishore P A K and Padma Priya K, "LOW POWER CLOCK DISTRIBUTION NETWORK USING CLOCK PAIRED SHARED FLIP FLOP," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 5, No. 4, pp. 18-27, October 2016.