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S R Patil and Naseeruddin
Department of ECE, BITM, Bellary, Karnataka, India.

Abstract— A low-voltage Low-Dropout (LDO) regulator that converts an input of 1 V to an output of 0.85-0.5 V, with 90-nm CMOS technology is proposed. A simple symmetric operational transconductance amplifier is used as the Error Amplifier (EA), with a current splitting technique adopted to boost the gain. This also enhances the closed-loop bandwidth of the LDO regulator. In the rail-to-rail output stage of the EA, a power noise cancellation mechanism is formed, minimizing the size of the power MOS transistor. Furthermore, a fast responding transient accelerator is designed through the reuse of parts of the EA. These advantages allow the proposed LDO regulator to operate over a wide range of operating conditions while achieving 99.94% current efficiency, a 28-mV output variation for a 0-100 mA load transient, and a power supply rejection of roughly 50 dB over 0-100 kHz. The area of the proposed LDO regulator is only 0.0041 mm2, because of the compact architecture.

Index Terms— Fast transient response, High power supply rejection, Low-Dropout (LDO) regulator, Low-voltage, Small area

Cite: S R Patil and Naseeruddin, " DESIGN OF A LOW-VOLTAGE LOW-DROPOUT REGULATOR," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 4, No. 1, pp. 30-39, January 2015.