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IJEETC 2024 Vol.13(3): 224-228
doi: 10.18178/ijeetc.13.3.224-228

A Study of High-Speed Hamming Distance Detection Circuit Utilizing a Neuron CMOS Inverter

Daishi Nishiguchi1,*, Yujiro Harada2, Mitsutoshi Yahara3, and Kuniaki Fujimoto4
1. Research Institute of Science and Technology, Tokai University, Kanagawa, Japan
2. Department of Electrical and Electronics Engineering, National Institute of Technology, Kurume College, Fukuoka, Japan
3. Department of Community and Social Studies, Tokai University, Kumamoto, Japan
4. Department of Human Information Engineering, Tokai University, Kumamoto-shi, Kumamoto, Japan
Email: daishi@tsc.u-tokai.ac.jp (D.N.), y-harada@kurume-nct.ac.jp (Y.H.), yahara@tokai.ac.jp (M.Y.), fujimoto@tokai.ac.jp (K.F.)
*Corresponding author

Manuscript received October 10, 2023; revised December 5, 2023; accepted December 29, 2023.

Abstract—This study tackles the challenge of optimizing associative memory for efficient data retrieval from large databases, crucial in real-time processing. The authors specifically address the issue of increased detection time in the minimum Hamming distance search associative memory, particularly as the number of data bits grows. This memory system utilizes Hamming distance as a key metric to identify the most similar reference data. Our contribution is the development of a new Hamming distance detection circuit employing neuron Complementary Metal Oxide Semiconductor (CMOS) inverters. This proposed circuit significantly outperforms existing models in terms of operational speed. The effectiveness and improved performance of the circuit are validated through simulations using HSPICE, a type of Simulation Program with Integrated Circuit Emphasis (SPICE) demonstrating its potential for more efficient real-time data retrieval applications.

Index Terms—associative memory, hamming distance, high-speed

Cite: Daishi Nishiguchi, Yujiro Harada, Mitsutoshi Yahara, and Kuniaki Fujimoto, "A Study of High-Speed Hamming Distance Detection Circuit Utilizing a Neuron CMOS Inverter," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 13, No. 3, pp. 224-228, 2024. doi: 10.18178/ijeetc.13.3.224-228

Copyright © 2024 by the authors. This is an open access article distributed under the Creative Commons Attribution License (CC BY-NC-ND 4.0), which permits use, distribution and reproduction in any medium, provided that the article is properly cited, the use is non-commercial and no modifications or adaptations are made.