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ASIC Design and Implementation of 25 Gigab it Ethernet Transceiver with RS_FEC

Eman Salem1, Abdelhalim Zekry2, and Radwa M. Tawfeek1
1. Benha Faculty of Engineering, Benha University, Electrical Engineering Department - Egypt
2. Faculty of Engineering, Ain Shams University, Electronics and Communications Department –Egypt

Abstract—This paper presents ASIC (application specific integrated circuit) design and implementation of a high-speed 25 Gigabit Ethernet (GE) transceiver with ForwardError Correction (FEC) layer utilizing Reed Solomon (RS) (255, 239) code. We designed 25 GE to provide a simpler and more cost-efficient path to future Ethernet speeds, including 50 Gbps, 100 Gbps, and beyond. Until recently, a majority of available 100 GbE implementations used ten lanes of 10 GE. But utilizing 4-lanes (4×25 G) is more economical. We also improved the design by insert FEC devices to provide error correction ability for optical communication system. RS (255, 239) CODEC (encoder/decoder) architecture was designed in parallel to be suitable for high-speed fiber-optic system. The proposed channel consists of 8 RS COCEC in parallel. Parallelizing and pipelining allow data to be transmitted at high fiberoptical rates and received at correspondingly high rates with minimal latency. The overall system was implemented by 45 nm CMOS standard cell technology of ten layers with standard cells in a supply voltage 1.1 V. In this design, at most 8 bytes errors for each data frame (255 Bytes) under the demanded working frequency 25 GHz can be detected and corrected. The fully VHDL codes for a complete system were synthesized by Synopsys design compiler based on NCSU 45 nm CMOS technology. Electronic Design Automation (EDA) tools are used for simulation, synthesis, physical implementation and errors check. The implementation results obtained are exhibited during this paper. It shows that the designed structure has merits such as high efficiency and low power consumption ensuring good coding performance than previous designs. 
Index Terms—25Gbps Ethernet, physical layer PHY, reed solomon, FEC, VLSI technology, synopsys, ModelSim, VHDL, System on Chip (SOC) encounter, cadence, virtuoso

Cite: Eman Salem, Abdelhalim Zekry, and Radwa M. Tawfeek, "ASIC Design and Implementation of 25 Gigab it Ethernet Transceiver with RS_FEC," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 9, No. 3, pp. 148-155, May 2020. Doi: 10.18178/ijeetc.9.3.148-155

Copyright © 2020 by the authors. This is an open access article distributed under the Creative Commons Attribution License (CC BY-NC-ND 4.0), which permits use, distribution and reproduction in any medium, provided that the article is properly cited, the use is non-commercial and no modifications or adaptations are made.