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Performance Analysis of High-k Dielectric Based Silicon Nanowire Gate-All-Around Tunneling FET

Shashi K. Dargar and Viranjay M. Srivastava
Department of Electronic Engineering, Howard College, University of KwaZulu-Natal, Durban-4041, South Africa

Abstract—The Tunnel Field Effect Transistors (TFETs) are used as a promising candidate in low power applications at the nanometer scale primarily because the conventional Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) approaches the physical and thermal limits. In this research work, a TFET device with cylindrical gate-all-around structure (Si-nanowire as channel and HfO2 as a high-k dielectric gate oxide) has been designed and simulated for the analyzing short channel effects. First, the effect of variation in channel lengths (100 nm to 180 nm) of the TFET is analyzed. Further, the gate oxide thickness variations in the ranging 3 nm to 6.5 nm at different channel length are presented. As a result, the device displays Drain Induced Barrier Lowering (DIBL) as low as of 7.1 mV/V to 10.26 mV/V, low Subthreshold Swing (SS) in the range of 19.91 mV/decade to 34.36 mV/decade and a reasonable current ratio (ION/IOFF) in the ranges of 2.9×106 to 7.8×109 which suggest the usability of the device in ultra-low power switching applications. 

Index Terms—Band-to-band tunneling, GAA structure, nanotechnology, Si-nanowire, tunnel FET, VLSI

Cite: Shashi K. Dargar and Viranjay M. Srivastava, "Performance Analysis of High-k Dielectric Based Silicon Nanowire Gate-All-Around Tunneling FET," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 8, No. 6, pp. 340-345, November 2019. Doi: 10.18178/ijeetc.8.6.340-345