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A Fabric IP Netlist Generator for a Compiler-Approach to Fabric Integration

Arcel R. Salem 1, Erwil V. Pasia 2, and Allenn C. Lowaton 1
1. MSU-IIT/EECE, Iligan City, Philippines
2. Lattice Semiconductor Corporation, Muntinlupa City, Philippines
Abstract—Integrating fabric intellectual property (IP) netlists in field programmable gate array (FPGA) development can be very time-consuming especially if the design complexity and density increased significantly and the integration is done manually. Another issue in most integration techniques available is that it does not have a dedicated fabric IP netlists generator which makes the integration more tedious especially if there are changes and iterations needed in the design development like changing the design density. This paper introduces a fabric IP netlist generator that uses a compiler-approach to fabric integration. The compiler automatically connects the IP blocks and generates a fabric IP netlist depending on the user-input parameters. This tool provides the flexibility of changing the fabric IP array sizes and the IPs to be connected depending on the specifications required. It enables designers to design large densities of fabric IPs and also speeds up the FPGA development. 
 
Index Terms—compiler, CDL netlist, fabric IP, FPGA, integration, IP, Verilog netlist

Cite: Arcel R. Salem, Erwil V. Pasia, and Allenn C. Lowaton, "A Fabric IP Netlist Generator for a Compiler-Approach to Fabric Integration," International Journal of Electrical and Electronic Engineering & Telecommunications,  Doi: 10.18178/ijeetc.180213
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