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Fast Performance Pipeline Re-Configurable FFT Processor Based on Radix-2<sup>2</sup> for Variable Length N

Manish Bansal and Sangeeta Nakhate
MANIT EC Department, Bhopal, India
Abstract—This paper proposes fast performance reconfigurable pipeline variable points FFT processor design. This design is proposed for variable N points whose values can be 8, 16, 32, 64, 128, 256 and 512 sample points. Hence, the proposed reconfigurable design can be used for different points OFDM applications rather using different designs. The proposed implementation design uses Radix-22 common factor algorithm (CFA) algorithm and SDF architecture. Radix-22 CFA algorithm reduces the number of twiddle factors compared to Radix-4 and Radix-2 and utilizes Radix-2 butterfly structure whose complexity is very low. SDF architecture uses less memory and utilizes multipliers fully compared to others. The frequency of proposed design is varied with the FFT points N. The proposed design is synthesized successfully using XST of Xilinx ISE 14.1 and simulated using ModelSim & MATLAB tool to verify results. Synthesized results of the proposed design for 512 points are 155.9 MHz max frequency, slice used 1795, slices Flip Flops used 1028 and LUTs used 3335 which are approximately 37% higher, 35%, 19%, 27% lesser in ratio than convention FFTs. 
 
Index Terms—FFT, Radix-22 CFA, complex multiplier, SDF, OFDM

Cite: Manish Bansal and Sangeeta Nakhate, "Fast Performance Pipeline Re-Configurable FFT Processor Based on Radix-2<sup>2</sup> for Variable Length N," International Journal of Electrical and Electronic Engineering & Telecommunications,  Doi: 10.18178/ijeetc.180401
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