Abstract—This paper presents a new fully parallel stochastic Low-Density Parity-Check (LDPC) decoding approach, to implement field programmable gate array (FPGA) based LDPC-decoders. The improved configuration is synthesised to optimize the FPGA logic utilisation and to decrease the decoding latency. To attain the target complexity reduction, the routing of the proposed sub variable node (VN) internal memory is designed to exploit only one slice distributed RAM. Furthermore, an efficient VN initialization, using the channel input probability, is performed to improve the decoder convergence, without requiring additional resources and without incorporating output saturated-counters. The Xilinx FPGA implementation, of (48, 24), (200, 100) and (1024, 512) regulars codes, shows that the proposed decoding approach reach high performance along with reduction of logic utilisation.

Index Terms—Low-Density Parity-Check (LDPC) decoder, stochastic decoding, field programmable gate array (FPGA)
 

Cite: Ghania Zerari, Abderrezak Guessoum, and Rachid Beguenane, "A New Design for Reducing Logic Utilizations in FPGA-Based Stochastic LDPC Decoders," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 6, No. 4, pp. 1-5, October 2017. DOI: 10.18178/ijeetc.6.4.1-5