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Sithara Sha and Shajimon K John
VLSI & Embedded Systems, ECE Department, SAINTGITS College of Engineering, Kottayam.

Abstract—Modulo 2n + 1 arithmetic has a variety of applications in several fields like cryptography, pseudorandom number generation, eliminating round-off errors in convolution computations, etc. Residue Number System (RNS) represents a number in the range of [0, 2n] using n + 1 bits. The RNS is an arithmetic system which decomposes a number into parts (residues) and performs arithmetic operations in parallel for each residue without the need of carry propagation among them, leading to significant speed up over the corresponding binary operations. RNS is well suited to applications that are rich of addition/subtraction and multiplication operations and has been adopted in the design of digital signal processors. The complexity of modulo 2n + 1 arithmetic operation such as addition and multiplication can be reduced by designing an efficient modulo 2n + 1 adder and modulo 2n + 1 multiplier. Both the addition and multiplication are combined together to form a multiply and accumulate (MAC) unit. Diminished-one number representation is employed in this MAC unit. In the diminished-one number system, each number X is represented by X* = X – 1 and the representation of 0 is treated in a special way. Therefore, diminished-one modulo 2n + 1 circuits require only n bits for their number representations. An efficient modulo 2n + 1 MAC unit is presented in this paper. A diminishedone modulo 2n + 1 adder using parallel-prefix tree for carry computation and modulo 2n + 1 multiplier based on dadda tree architecture is used for MAC architecture. The proposed MAC unit is analysed using various tools like ModelSim 10.1b for logical verification and for synthesizing Leonardo Spectrum LS 2009 a_6.

Index Terms—RNS, Modulo 2n + 1 arithmetic; Diminished-one number representation, Modulo adder, Modulo multiplier

Cite: Sithara Sha and Shajimon K John, "MODULO 2n + 1 MAC UNIT," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 2, No. 4, pp. 21-29, October 2013.