Abstract—This paper presents a delay measurement techniques using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18 m process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.

Index Terms—Delay estimation, Design For Testability (DFT), Integrated circuit measurements, Semiconductor device reliability, Signature register

Cite: P M Nasir Hussain and G V Suresh Babu, "DESIGN OF SIGNATURE REGISTERS USING SCAN FLIP-FLOPS FOR ON-CHIP DELAY MEASUREMENT," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 2, No. 4, pp. 87-100, October 2013.