Dalian Maritime University, China
It is my honor to be the editor-in-chief of IJEETC. The journal publishes good papers which focous on the advanced researches in the field of electrical and electronic engineering & telecommunications.
Abstract—Hybrid RISC Controllers are used in present day embedded systems in order to increase the
flexibility and performance. These processors requires efficient test patterns to detect faults.In
present days there are number of techniques are developed to detect the permanent faults in
different processors Software-Based Self-Test (SBST) methods are used for automatic
generation of test programs (SBST) programs. But by using these techniques test duration is
high and even if every line of code has been executed the Device Under Test (DUT) may not be
correct. VHDL Verification Methodology (VVM) provides a way of collecting the values of nodes
in the verification environment and helps to decide when verification is completed. The the code
size and test duration are measured.
Index Terms—Hybrid RISC Controllers, VHDL Verification Methodology (VVM), Device Under
Test (DUT), Software-Based Self-Test (SBST)
Cite: M Kamaraju and Y Divyasree, "A SURVEY ON VVM BASED TEST PROGRAMS
FOR HYBRID RISC CONTROLLER," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 6, No. 2, pp. 104-108, April 2017.
Copyright © 2012-2021. International Journal of Electrical and Electronic Engineering & Telecommunications, All Rights Reserved