Abstract—Single event transients (SETs) have become increasingly problematic for both combinational and sequential VLSI circuits in the deep submicron technology (DSM). This is due to continuously decreasing feature sizes, lower supply voltages and higher operating frequencies. Many critical applications such as biomedical, space and military electronics as well as several mainstream computing applications demand reliable circuit functionality. Therefore, the circuits used in these application must be tolerant to SEU/SET events and therefore, these circuits are designed using circuit hardening approaches. Hardening by design techniques based on increasing the amount of charge representing the bit and redundancy techniques have been used over the years. In this paper, we present a novel design strategy to reduce the impact of radiation-induced single event transients (SET) on combinational logic circuits. This design style achieves SET mitigation by using C element and strengthening the sensitive output node. In order to check the accuracy of our proposal, we compare it with others techniques for hardening radiation at the transistor level against a single event transient. Simulation results show that the proposed method has a good soft error tolerance capability as well as better noise immunity.

Index Terms—Single event transients (SET), Radiation hardening, Soft errors, C Element, Strengthening

Cite: Tokala Vinay Reddy and Sangeeta Nakhate, "SINGLE EVENT TRANSIENT HARDENING TECHNIQUE FOR LOGIC GATES BASED ON RADIATION HARDENING BY DESIGN (RHBD)," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 6, No. 2, pp. 50-58, April 2017.