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Shilpa Saxena and Rajesh Mehra
Department of Electronics & Communication Engineering, NITTTR, Chandigarh, UT, India.

Abstract—In this paper the stable and power-efficient method is presented to design and implement Static- RAM Cell. Static-RAM is one of the essential building block for the VLSI design. Due to their higher speed Static-RAM based Cache memories and System-on-chips are commonly used. Due to device scaling there are several design challenges for Static-RAM design in nanometer technology. The Static-RAM implementation is based on 45 nm CMOS submicron technology. The transmission gates are used in the access path of the SRAM Cell and the Sleep transistors power gating technique is used for low leakage power and high performance. The transient and dc analysis of the proposed ST13T Static-RAM cell has been obtained for high performance. It can be observed from the results that the percentage reduction of 33.66% in power dissipation, 62.18% in noise, 10.20% in delay and 38.14% in PDP is obtained for the proposed ST13T circuit with power gating technique are that shows the high performance for Static-RAM Cell.

Index Terms—CMOS integrated circuit, Integration VLSI, Layout, Logic design, Nanometers, Static-RAM chips

Cite: Shilpa Saxena and Rajesh Mehra, "HIGH PERFORMANCE AND LOW POWER SRAM CELL DESIGN USING POWER GATING TECHNIQUE," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 5, No. 3, pp. 35-47, July 2016.