Dalian Maritime University, China It is my honor to be the editor-in-chief of IJEETC. The journal publishes good papers which focus on the advanced researches in the field of electrical and electronic engineering & telecommunications.
2024-03-15
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2024-02-02
Abstract—The voltage controlled oscillator is one of the most important building block of the PLL based frequency synthesizer. This paper presents two design of three stage CMOS Ring VCO for PLL based Frequency Synthesizer. Ring VCO simply consists of cascaded inverters. The performance comparison is done in terms of output frequency, power dissipation and supply voltage for two different technologies. First design comprises of three stage ring VCO designed in 18 μm CMOS technology and achieves a high frequency of 5.2 GHz with a power dissipation of 152 μW under the supply voltage of 1.8 V. In the second design, a three stage ring VCO is designed in 90 nm CMOS technology and achieves a frequency of 32 GHz with a power dissipation of 132 W under the supply voltage of 1.2 V. Index Terms—VCO, Ring oscillator, CMOS, PLL, Inverter, Power dissipation, Time delay, Frequency
Cite: Poonam Sachdeva and Ankita Aggarwal, "DESIGN OF CMOS RING VCO FOR PLL BASED FREQUENCY SYNTHESIZER," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 5, No. 2, pp. 73-79, April 2016.