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K Sarala and N Suresh Babu
Department of ECE, Chirala Engineering College, Chirala, Andhra Pradesh 523157, India

Abstract— AS CMOS technology scales down to nano scale and memories are combined with an increasing number of electronic systems, the soft error rate in memory cells is rapidly increasing, especially when memories operate in space environments due to ionizing effects of atmospheric neutron, alpha-particle, and cosmic rays. Although single bit upset is a major concern about memory reliability, Multiple Cell Upsets (MCUs) have become a serious reliability concern in some memory applications. In order to make memory cells as fault-tolerant as possible, some Error Correction Codes (ECCs) have been widely used to protect memories against soft errors for years. For example, the Bose Chaudhuri Hocquenghem codes, Reed-Solomon codes, and Punctured Difference Set (PDS) codes have been used to deal with MCUs in memories. But these codes require more area, power, and delay overheads since the encoding and decoding circuits are more complex in these complicated codes. In this project due to introduction of parallel corrector block to enhance the performance of the corrector with less power consumption is proposed.

Index Terms— Fault-tolerant, Power consumption, Memory, Parallel corrector

Cite: K Sarala and N Suresh Babu, "REALIZATION OF POWER OPTIMIZED FAULT TOLERANT MEMORY PROTECTED ECC STRUCTURE," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 4, No. 4, pp. 22-30, October 2015.