Dalian Maritime University, China It is my honor to be the editor-in-chief of IJEETC. The journal publishes good papers which focus on the advanced researches in the field of electrical and electronic engineering & telecommunications.
2024-03-15
2024-03-06
2024-02-02
Abstract— To design a low power processor, low power Arithmetic and Logic Unit (ALU) is required, since ALU is one of the core components and most power hungry sections in a microprocessor that carries out the arithmetic and logic operations. Clock gating is the power saving technique used for low power design, it switches off the module which is not active as decided by selection line. This techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Control signal gating technique provides power saving by reducing unnecessary switching activity on datapath buses, when a bus is not going to be used and it will be held in a quiescent state by stopping the propagation of switching activity through the module(s) driving the bus. For designing a proposed Power Efficient ALU, both the clock gating and the control-signal gating techniques are introduced for minimizing the clock power and to reduce the unnecessary switching activity of data path. Functionality of proposed ALU is verified by using Xilinx tool and power analysis is carried out by using Xilinx X’Power analysis tool. Index Terms— Clock gating, Control-signal gating, Data buses, Low power, Switching activity, Dynamic power
Cite: Anil Kumar Yadav and Mohammed Aneesh Y, " POWER EFFICIENT ALU DESIGN WITH CLOCK AND CONTROL-SIGNAL GATING TECHNIQUE," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 4, No. 2, pp. 8-15, April 2015.