Nanyang Technological University, Singapore
It is my honor to be the editor-in-chief of IJEETC. The journal publishes good papers which focous on the advanced researches in the field of electrical and electronic engineering & telecommunications.
Abstract—Adder is one among the basic arithmetic operates. Currently implementing a high speed VLSI style could be an important topic and as adders are utilized in various fields of applications, coming up with a high speed adder is one among the necessary facets. In this paper we designed and enforced a high speed KoggeStone parallel prefix adder of 8, 16, 32 and 64 bit to be meted out and compared with Carry Look Ahead adder (CLA) and Carry Skip Adder (CSA) and also pointed out the potency of KoggeStone adder with relevance delay victimization using Xilinx ISE 14.7.
Index Terms—:64 bit high speed adder, KoggeStone adder, CLA, CSA
Cite: Raghumanohar Adusumilli and Vinod Kumar K, "DESIGN AND IMPLEMENTATION OF A HIGH SPEED 64 BIT KOGGE-STONE ADDER USING VERILOG HDL," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 4, No. 1, pp. 13-18, January 2015.
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