Abstract—In this paper a new approach termed as space-time scheduling (STS) strategy is introduced where both area and performance evaluations are improved simultaneously. To reduce the area the proposed architecture is designed in such a way that the same architecture is used for both 1D and 2D applications using cascading approaches. In that it can calculate first-dimensional and second-dimensional transformations simultaneously in single 1-D discrete cosine transform (DCT) core to reach less hardware utilization. The DA-precision bit length is chosen as 9 bits instead of the traditional 12 bits to reduce the size of the chip without any degradation of the performance. Modules in the 1-D DCT core, including the modified two-input butterfly (MBF2), the pre-reorder, the process element even (PEE), the process element odd (PEO), and the post reorder share the hardware resources in order to reduce the area. The adders in the design are replaced by a low power and area efficient reversible Vedic adders to improve the overall performance of the system.

Index Terms—Keywords: Discrete cosines transform (DCT), Reversible logic and Vedic mathematics

Cite: Thamanam Sowjanya and N Suresh Babu, "A HIGH PERFORMANCE VIDEO TRANSFORM ENGINE BY USING SPACE-TIME SCHEDULING STRATEGY REVERSIBLE VEDIC GATES," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 3, No. 4, pp. 95-100, October 2014.