Abstract—This paper proposes a low-cost high-throughput Multi-standard transform (MST) core, which can support MPEG-1/2/4 (8×8), H.264 (8×8, 4×4), and VC-1 (8×8, 8×4, 4×8, 4×4) transforms. Common sharing distributed arithmetic (CSDA) combines factor sharing and distributed arithmetic sharing techniques, efficiently reducing the number of adders for high hardwaresharing capability. This achieves a 44.5% reduction in adders in the proposed MST, compared with the direct implementation method. With eight parallel computation paths, the proposed MST core has an eightfold operation frequency throughput rate. Measurements show that the proposed CSDAMST core achieves a high-throughput rate of 1.28 G-pels/s, supporting the (4928×2048@24 Hz) digital cinema or ultrahigh resolution format. This is possible only with 30k gate counts when implemented in a TSMC 0.18-μm CMOS process. The CSDA-MST core thus achieves a high-throughput rate supporting Multi-standard transformations at low cost.

Index Terms—Keywords: Common sharing distributed arithmetic (CSDA), discrete cosine transform (DCT), Integer transform, Multi-standard transform (MST)

Cite: Thammisetty Arun Kumar and N Suresh Babu, "POWER AND AREA OPTIMAL IMPLEMENTATION OF 2D-CSDA FOR MULTI STANDARD CORE," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 3, No. 4, pp. 148-159, October 2014.