Abstract—Multiplier design is always a challenging task; however many designs are proposed, the user needs demands much more optimized ones. Vedic mathematics provides some algorithms that evaluate fast results, both in mental calculations or hardware design. Power dissipation is continously reduced by the use of Reversible logic. The reversible Urdhva Tiryakbhayam Vedic multiplier is one such multiplier which is effective both in terms of speed and power. In this paper the modified design increase the performance by maintain the design functionality without any degradation. The Total Reversible Logic Implementation Cost (TRLIC) evaluate the proposed design. This multiplier has application over designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios, wireless communications.

Index Terms—Keywords: Revesible Gates, Urdhva Tiryakbhayam , Vedic mathematics

Cite: Degala Santhi Priya and K Hari Krishna, "IMPLEMENTATION OF SPEED AND POWER OPTIMIZED VEDIC MULTIPLIERS USING REVERSIBLE GATE APPROACH," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 3, No. 4, pp. 107-117, October 2014.