Abstract—This project deals with the comparison of the VLSI design of the Carry Look-Ahead Adder (CLAA) based 32-bit unsigned integer multiplier and the VLSI design of the carry select adder (CSLA) based 32-bit unsigned integer multiplier. Both the VLSI design of multiplier mUltiplies two 32-bit unsigned integer values and gives a product term of 64-bit values. The CLAA based multiplier uses the delay time of 99 ns for performing mUltiplication operation where as in CSLA based multiplier also uses nearly the same delay time for mUltiplication operation. But the area needed for CLAA multiplier is reduced to 31% by the CSLA based multiplier to complete the multiplication operation. These multipliers are implemented using Altera Quartus II and timing diagrams are viewed through avan waves. ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance.

Index Terms—Keywords: CLAA, CSLA, Delay, Area, Array multiplier, VHDL modeling, Simulation

Cite: Veersh B Jalihal and Naseeruddin, "DESIGN AND IMPLEMENTATION OF 32 BIT UNSIGNED MULTIPLIER USING CLAA, CSLA, ETA," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 3, No. 3, pp. 111-118, July 2014.