Abstract—In present generation, VLSI systems and their design became so much important in the Electronic Engineering. As the VLSI design is the basis for electronic components, one should optimise the constraints. For high performance systems such as digital signal processors and microprocessors, Multiplier is the key hardware block. In designing VLSI systems, the main criteria of interest are high speed, low power, less area, low cost. Many researchers have tried and are trying to design multipliers which offer either of the following design targets-high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier, thus making them suitable for various compact VLSI implementations. Improving speed results always in larger areas. So, this paper provides the techniques that optimise the area and speed up the multiplication process.

Index Terms—Multiplier, Wallace tree structure, Compressors, Sklansky adder

Cite: K Padma Priya, P Sai Arun Kumar, B Mounika, P Lavanya, D Sivananda Das and B Buchi Babu, "REVIEW ON OPTIMIZATION TECHNIQUES OF WALLACE TREE MULTIPLIER," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 3, No. 2, pp. 32-40, April 2014.