Abstract—This paper presents a technique for minimizing sub threshold leakage current using stacked sleep technique. Comparison is made with conventional CMOS, Sleepy stack, Forced stack, Sleepy keeper and the proposed body biased keeper which were analyzed using BSIM 4 model. The proposed technique dissipates lesser static power and lesser delay product compared to the previous technique. An improvement of 1.2X was observed in static power dissipation in comparison with conventional approach, thus maintaining the state of art of the logic in the digital circuit.

Index Terms—Sub threshold leakage, Conventional CMOS, Sleepy stack, Forced stack, Body biased keeper, Sleepy keeper, BSIM 4

Cite: Anjana R and Ajay Kumar Somkuwar, "MINIMIZING THE SUB THRESHOLD LEAKAGE FOR HIGH PERFORMANCE CMOS CIRCUITS USING NOVEL STACKED SLEEP TRANSISTOR TECHNIQUE," International Journal of Electrical and Electronic Engineering & Telecommunications, Vol. 1, No. 1, pp. 76-82, October 2012.